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      CPLDs (Complex Programmable Logic Devices)

      CPLDs (Complex Programmable Logic Devices)
      ModelDescriptionBrandLeadingConditionPriceAction
      CPLDs (Complex Programmable Logic Devices)
      XC95108-10PC84C
      The XC95108-10PC84C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. Power dissipation can be reduced in the XC95108-10PC84C by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.Operating current for each design can be approximated for specific operating conditions using the following equation:ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) fWhere:MCHP = Macrocells in high-performance modeMCLP = Macrocells in low-power modeMC = Total number of macrocells usedf = Clock frequency (MHz)• 7.5 ns pin-to-pin logic delays on all pins• fCNT to 125 MHz• 108 macrocells with 2,400 usable gates• Up to 108 user I/O pins• 5V in-system programmable- Endurance of 10,000 program/erase cycles- Program/erase over full commercial voltage and temperature range• Enhanced pin-locking architecture• Flexible 36V18 Function Block- 90 product terms drive any or all of 18 macrocells within Function Block- Global and product term clocks, output enables, set and reset signals• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support• Programmable power reduction mode in each macrocell• Slew rate control on individual outputs• User programmable ground pin capability• Extended pattern security features for design protection• High-drive 24 mA outputs• 3.3V or 5V I/O capability• Advanced CMOS 5V FastFLASH™ technology• Supports parallel programming of more than one XC9500 concurrently• Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages
      		OTHERIn StockNew Sealed Under Guarantee
      XC9572XL-10VQG64I
      Please note this product is Non-Cancellable and Non-Returnable (NCNR)Optimized for high-performance 3.3V systems- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)- Pb-free available for all packages- Lower power operation- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS FastFLASH technology• Advanced system features- In-system programmable- Superior pin-locking and routability with FastCONNECT II switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with individual product-term allocation- Local clock inversion with three global and one product-term clocks- Individual output enable per output pin with local inversion- Input hysteresis on all user and boundary-scan pin inputs- Bus-hold circuitry on all user pin inputs- Supports hot-plugging capability- Full IEEE Std 1149.1 boundary-scan (JTAG)support on all devices• Four pin-compatible device densities- 36 to 288 macrocells, with 800 to 6400 usable gates• Fast concurrent programming• Slew rate control on individual outputs• Enhanced data security features• Excellent quality and reliability- 10,000 program/erase cycles endurance rating- 20 year data retention• Pin-compatible with 5V core XC9500 family in common package footprints
      		OTHERIn StockNew Sealed Under Guarantee
      XC9536XL-10VQG64C
      Please note this product is Non-Cancellable and Non-Returnable (NCNR) Optimized for high-performance 3.3V systems- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)- Pb-free available for all packages- Lower power operation- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS FastFLASH technology• Advanced system features- In-system programmable- Superior pin-locking and routability with FastCONNECT II switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with individual product-term allocation- Local clock inversion with three global and one product-term clocks- Individual output enable per output pin with local inversion- Input hysteresis on all user and boundary-scan pin inputs- Bus-hold circuitry on all user pin inputs- Supports hot-plugging capability- Full IEEE Std 1149.1 boundary-scan (JTAG)support on all devices• Four pin-compatible device densities- 36 to 288 macrocells, with 800 to 6400 usable gates• Fast concurrent programming• Slew rate control on individual outputs• Enhanced data security features• Excellent quality and reliability- 10,000 program/erase cycles endurance rating- 20 year data retention• Pin-compatible with 5V core XC9500 family in common package footprints
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      XC9536-15PCG44 C
      Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support. See XCN07010 for details regarding this discontinuation, including device replacement recomendations for the XC9536XV CPLD.36 macrocells with 800 usable gatesAvailable in small footprint package44-pin VQFP (34 user I/O pins)Optimized for high-performance 2.5V systemsLow power operationMulti-voltage operationAdvanced system featuresIn-system programmableSuperior pin-locking and routability with Fast CONNECT™ II switch matrixExtra wide 54-input Function BlocksUp to 90 product-terms per macrocell with individual product-term allocationLocal clock inversion with three global and one product-term clocksIndividual output enable per output pinInput hysteresis on all user and boundary-scan pin inputsBus-hold circuitry on all user pin inputsFull IEEE Standard 1149.1 boundary-scan (JTAG)Fast concurrent programmingSlew rate control on individual outputsEnhanced data security featuresExcellent quality and reliability20 year data retentionESD protection exceeding 2,000VPin-compatible with 3.3V-core XC9536XL device in the 44-pin VQFP package
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      XC2C512-10FTG256I
      The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.Optimized for 1.8V systems- As fast as 7.1 ns pin-to-pin delays- As low as 14 μA quiescent current• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis- Multi-voltage I/O operation — 1.5V to 3.3V• Available in multiple package options- 208-pin PQFP with 173 user I/O- 256-ball FT (1.0mm) BGA with 212 user I/O- 324-ball FG (1.0mm) BGA with 270 user I/O- Pb-free available for all packages• Advanced system features- Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt-trigger input (per pin)- Unsurpassed low power management· DataGATE enable signal control- Four separate I/O banks- RealDigital 100% CMOS product term generation- Flexible clocking modes· Optional DualEDGE triggered registers· Clock divider (divide by 2,4,6,8,10,12,14,16)· CoolCLOCK- Global signal options with macrocell control· Multiple global clocks with phase selection permacrocell· Multiple global output enables· Global set/reset- Advanced design security- PLA architecture· Superior pinout retention· 100% product term routability across function block- Open-drain output option for Wired-OR and LED drive- Optional bus-hold, 3-state or weak pullup on selected I/O pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility- Hot Pluggable
      		OTHERIn StockNew Sealed Under Guarantee
      XC2C256-7FTG256I
      The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improvedThis device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK featureDataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.Table 1: I/O Standards for XC2C128(1)IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTTLVTTL3.33.3N/AN/ALVCMOS333.33.3N/AN/ALVCMOS252.52.5N/AN/ALVCMOS181.81.8N/AN/ALVCMOS15(2)1.51.5N/AN/AHSTL_11.51.50.750.75SSTL2_12.52.51.251.25SSTL3_13.33.31.51.5 Optimized for 1.8V systems- As fast as 5.7 ns pin-to-pin delays- As low as 13 μA quiescent current• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis.Refer to the CoolRunner™-II family data sheet forarchitecture description.- Multi-voltage I/O operation — 1.5V to 3.3V• Available in multiple package options- 100-pin VQFP with 80 user I/O- 144-pin TQFP with 118 user I/O- 132-ball CP (0.5mm) BGA with 106 user I/O- 208-pin PQFP with 173 user I/O- 256-ball FT (1.0mm) BGA with 184 user I/O- Pb-free available for all packages
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      XC6SLX16-2FTG256C
      The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs
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      XCR3128XL-6VQG100C
      The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the CoolRunner XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the CoolRunner XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.The CoolRunner XPLA3 family employs a full PLA structure for logic allocation within a function block. The PLA provides maximum flexibility and logic density, with superior pin locking capability, while maintaining deterministic timing.CoolRunner XPLA3 CPLDs are supported by Xilinx® WebPACK™ software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The CoolRunner XPLA3 family features also include the industry-standard, IEEE 1149.1, JTAG interface through which boundary-scan testing, In-System Programming (ISP), and reprogramming of the device can occur. The CoolRunner XPLA3 CPLD is electrically reprogrammable using industry standard device programmers.Fast Zero Power (FZP) design technique provides ultra-low power and very high speedTypical Standby Current of 17 to 18 μA at 25°CInnovative CoolRunner™ XPLA3 architecture combines high speed with extreme flexibilityBased on industry`s first TotalCMOS PLD — both CMOS design and process technologiesAdvanced 0.35μ five layer metal EEPROM process1,000 erase/program cycles guaranteed20 years data retention guaranteed3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interfaceFull Boundary-Scan Test (IEEE 1149.1)Fast programming timesSupport for complex asynchronous clocking16 product term clocks and four local control term clocks per function blockFour global clocks and one universal control term clock per deviceExcellent pin retention during design changesAvailable in commercial grade and extended voltage (2.7V to 3.6V) industrial grade5V tolerant I/O pinsInput register setup time of 2.5 nsSingle pass logic expandable to 48 product termsHigh-speed pin-to-pin delays of 5.0 nsSlew rate control per output100% routableSecurity bit prevents unauthorized accessSupports hot-plugging capabilityDesign entry/verification using Xilinx or industry standard CAE toolsInnovative Control Term structure provides:Asynchronous macrocell clockingAsynchronous macrocell register preset/resetClock enable control per macrocellFour output enable controls per function blockFoldback NAND for synthesis optimizationUniversal 3-state which facilitates "bed of nails" testingAvailable in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
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      XCR3064XL-6VQ100C
      he CoolRunner™ XPLA3 XCR3256XL device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.TotalCMOS Design Technique for Fast Zero PowerCoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution, both in process technology and design technique. These CPLDs employ a cascade of CMOS gates to implement their sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx CPLDs to offer devices that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Low power 3.3V 64 macrocell CPLD5.5 ns pin-to-pin logic delaysSystem frequencies up to 192 MHz64 macrocells with 1,500 usable gatesAvailable in small footprint packages44-pin VQFP (36 user I/O pins)48-ball CS BGA (40 user I/O pins)56-ball CP BGA (48 user I/O pins)100-pin VQFP (68 user I/O pins)Optimized for 3.3V systemsUltra-low power operationTypical Standby Current of 17 μA at 25°C5V tolerant I/O pins with 3.3V core supplyAdvanced 0.35 micron five layer metal EEPROM processFast Zero Power CMOS design technology3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)Advanced system featuresIn-system programmingInput registersPredictable timing modelUp to 23 available clocks per function blockExcellent pin retention during design changesFull IEEE Standard 1149.1 boundary-scan (JTAG)Four global clocksEight product term control terms per function blockFast ISP programming timesPort Enable pin for dual function of JTAG ISP pins2.7V to 3.6V supply voltage at industrial temperature rangeProgrammable slew rate control per macrocellSecurity bit prevents unauthorized accessRefer to XPLA3 family data sheet (DS012) for architecture description
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      XA2C128-7VQG100I
      The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II Automotive 128-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade• Guaranteed to meet full electrical specifications over TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)• Optimized for 1.8V systems• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis- Multi-voltage I/O operation — 1.5V to 3.3V• Available in the following package options- 100-pin VQFP with 80 user I/O- 132-ball CP (0.5 mm) BGA with 100 user I/O- Pb-free only for all packages• Advanced system features- Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt-trigger input (per pin)- Unsurpassed low power management· DataGATE enable (DGE) signal control- Two separate I/O banks- RealDigital 100% CMOS product term generation- Flexible clocking modes· Optional DualEDGE triggered registers· Clock divider (divide by 2,4,6,8,10,12,14,16)· CoolCLOCK- Global signal options with macrocell control· Multiple global clocks with phase selection per macrocell· Multiple global output enables· Global set/reset- Advanced design security- Open-drain output option for Wired-OR and LED drive- PLA architecture· Superior pinout retention· 100% product term routability across function block- Optional bus-hold, 3-state or weak pull-up on selected I/O pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels- Hot pluggable
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      XC95144XL-5TQ100C
      The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XL device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx® Virtex®, Spartan®-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9500XL devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9500XL architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times. Optimized for high-performance 3.3V systems- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)- Pb-free available for all packages- Lower power operation- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS FastFLASH technology• Advanced system features- In-system programmable- Superior pin-locking and routability with FastCONNECT II switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with individual product-term allocation- Local clock inversion with three global and one product-term clocks- Individual output enable per output pin with local inversion- Input hysteresis on all user and boundary-scan pin inputs- Bus-hold circuitry on all user pin inputs- Supports hot-plugging capability- Full IEEE Std 1149.1 boundary-scan (JTAG)support on all devices• Four pin-compatible device densities- 36 to 288 macrocells, with 800 to 6400 usable gates• Fast concurrent programming• Slew rate control on individual outputs• Enhanced data security features• Excellent quality and reliability- 10,000 program/erase cycles endurance rating- 20 year data retention• Pin-compatible with 5V core XC9500 family in common package footprints
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