| FPGAs (Field Programmable Gate Array) |
| | Xilinx® 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:Artix®-7 Family: Optimized for lowest cost and power with small form-factor packaging for the highest volume applications.Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power. | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capabilityFive platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table 1.The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. Low-cost, high-performance logic solution for high-volume,consumer-oriented applications• Densities up to 74,880 logic cells• SelectIO™ interface signaling• Up to 633 I/O pins• 622+ Mb/s data transfer rate per I/O• 18 single-ended signal standards• 8 differential I/O standards including LVDS, RSDS• Termination by Digitally Controlled Impedance• Signal swing ranging from 1.14V to 3.465V• Double Data Rate (DDR) support• DDR, DDR2 SDRAM support up to 333 Mb/s• Logic resources• Abundant logic cells with shift register capability• Wide, fast multiplexers• Fast look-ahead carry logic• Dedicated 18 x 18 multipliers• JTAG logic compatible with IEEE 1149.1/1532• SelectRAM™ hierarchical memory• Up to 1,872 Kbits of total block RAM• Up to 520 Kbits of total distributed RAM• Digital Clock Manager (up to four DCMs)• Clock skew elimination• Frequency synthesis• High resolution phase shifting | OTHER | In Stock | New Sealed Under Guarantee | | |
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| | The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays.Flexible Logic Resources- Up to 93,184 internal registers / latches with Clock Enable- Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers- Wide multiplexers and wide-input function support- Horizontal cascade chain and sum-of-products support- Internal 3-state bussing• High-Performance Clock Management Circuitry- Up to 12 DCM (Digital Clock Manager) modules ·Precise clock de-skew· Flexible frequency synthesis· High-resolution phase shifting- 16 global clock multiplexer buffers• Active Interconnect Technology- Fourth generation segmented routing structure- Predictable, fast routing delay, independent of fanout• SelectIO™-Ultra Technology- Up to 1,108 user I/Os- 19 single-ended and six differential standards- Programmable sink current (2 mA to 24 mA) per I/O- Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 μm CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.Refer to the Virtex 2.5V Field Programmable Gate Arrays commercial data sheet for more information on device architecture and timing specifications.Fast, high-density Field Programmable Gate Arrays- Densities from 50k to 1M system gates- System performance up to 200 MHz- 66-MHz PCI Compliant- Hot-swappable for Compact PCI• Multi-standard SelectIO™ interfaces- 16 high-performance interface standards- Connects directly to ZBTRAM devices• Built-in clock-management circuitry- Four dedicated delay-locked loops (DLLs) for advanced clock control- Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets• Hierarchical memory system- LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register- Configurable synchronous dual-ported 4k-bit RAMs- Fast interfaces to external high-performance RAMs• Flexible architecture that balances speed and density- Dedicated carry logic for high-speed arithmetic- Dedicated multiplier support- Cascade chain for wide-input functions- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset- Internal 3-state bussing- IEEE 1149.1 boundary-scan logic- Die-temperature sensor diode• Supported by FPGA Foundation™ and AllianceDevelopment Systems- Complete support for Unified Libraries, RelationallyPlaced Macros, and Design Manager- Wide selection of PC and workstation platforms• SRAM-based in-system configuration- Unlimited re-programmability- Four programming modes• 0.22 μm 5-layer metal process• 100% factory tested | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1.The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.• SelectIO™ signaling- Up to 633 I/O pins- Eighteen single-ended signal standards- Eight differential signal standards including LVDSand RSDS- Double Data Rate (DDR) support• Logic resources- Abundant logic cells with shift register capability- Wide multiplexers- Fast look-ahead carry logic- Dedicated 18 x 18 multipliers- JTAG logic compatible with IEEE 1149.1/1532• SelectRAM™ hierarchical memory- Up to 1,728 Kbits of total block RAM- Up to 432 Kbits of total distributed RAM• Digital Clock Manager (four DCMs)- Clock skew elimination- Frequency synthesis- High-resolution phase shifting | OTHER | In Stock | New Sealed Under Guarantee | | |
| | he Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,XCS05 approach and in many cases are equivalent to mask programmed ASIC devices.By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. In-System Programmable PROMs for Configuration of Xilinx® FPGAs• Low-Power Advanced CMOS NOR Flash Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (–40°C to +85°C)• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing• JTAG Command Initiation of Standard FPGA Configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Xilinx® Virtex® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at VCCINT = 0.85V, using -2LE devices, the speed specification for the L devices is the same as the -2I speed grade. When operated at VCCINT = 0.72V, the -2LE performance and static and dynamic power is reduced.DC and AC characteristics are specified in extended (E), industrial (I), and military (M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range. Absolute Maximum RatingsRecommended Operating ConditionsDC Characteristics Over Recommended Operating ConditionsQuiescent Supply CurrentThe recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements.For devices with HBM, the HBM power supplies can be powered on/off after or in-parallel with the core power supplies. The required power-on sequence is VCCAUX_HBM and VCCINT_IO followed by VCC_HBM/VCC_IO_HBM. VCC_IO_HBM must be connected to VCC_HBM. VCCAUX_HBM must be equal to or higher than VCC_HBM at all times.The recommended power-off sequence is the reverse of the power-on sequence. The recommended power-on sequence to achieve minimum current draw for the GTY or GTM transceivers is VCCINT, VCCINT_GT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VCCINT_GT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. When VCCINT and VCCINT_GT have the same recommended operating conditions, VCCINT and VCCINT_GT can be connected to the same power regulation circuit. When VCCINT and VCCINT_GT are connected to separate regulation circuits, VCCINT_GT must be within the recommended operating condition before device configuration.The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,XCS05 approach and in many cases are equivalent to mask programmed ASIC devices.By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. In-System Programmable PROMs for Configuration of Xilinx® FPGAs• Low-Power Advanced CMOS NOR Flash Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (–40°C to +85°C)• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing• JTAG Command Initiation of Standard FPGA Configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
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