| FPGAs (Field Programmable Gate Array) |
| | Xilinx® 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:Artix®-7 Family: Optimized for lowest cost and power with small form-factor packaging for the highest volume applications.Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power. | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capabilityFive platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table 1.The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. Low-cost, high-performance logic solution for high-volume,consumer-oriented applications• Densities up to 74,880 logic cells• SelectIO™ interface signaling• Up to 633 I/O pins• 622+ Mb/s data transfer rate per I/O• 18 single-ended signal standards• 8 differential I/O standards including LVDS, RSDS• Termination by Digitally Controlled Impedance• Signal swing ranging from 1.14V to 3.465V• Double Data Rate (DDR) support• DDR, DDR2 SDRAM support up to 333 Mb/s• Logic resources• Abundant logic cells with shift register capability• Wide, fast multiplexers• Fast look-ahead carry logic• Dedicated 18 x 18 multipliers• JTAG logic compatible with IEEE 1149.1/1532• SelectRAM™ hierarchical memory• Up to 1,872 Kbits of total block RAM• Up to 520 Kbits of total distributed RAM• Digital Clock Manager (up to four DCMs)• Clock skew elimination• Frequency synthesis• High resolution phase shifting | OTHER | In Stock | New Sealed Under Guarantee | | |
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| | The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays.Flexible Logic Resources- Up to 93,184 internal registers / latches with Clock Enable- Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers- Wide multiplexers and wide-input function support- Horizontal cascade chain and sum-of-products support- Internal 3-state bussing• High-Performance Clock Management Circuitry- Up to 12 DCM (Digital Clock Manager) modules ·Precise clock de-skew· Flexible frequency synthesis· High-resolution phase shifting- 16 global clock multiplexer buffers• Active Interconnect Technology- Fourth generation segmented routing structure- Predictable, fast routing delay, independent of fanout• SelectIO™-Ultra Technology- Up to 1,108 user I/Os- 19 single-ended and six differential standards- Programmable sink current (2 mA to 24 mA) per I/O- Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 μm CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.Refer to the Virtex 2.5V Field Programmable Gate Arrays commercial data sheet for more information on device architecture and timing specifications.Fast, high-density Field Programmable Gate Arrays- Densities from 50k to 1M system gates- System performance up to 200 MHz- 66-MHz PCI Compliant- Hot-swappable for Compact PCI• Multi-standard SelectIO™ interfaces- 16 high-performance interface standards- Connects directly to ZBTRAM devices• Built-in clock-management circuitry- Four dedicated delay-locked loops (DLLs) for advanced clock control- Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets• Hierarchical memory system- LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register- Configurable synchronous dual-ported 4k-bit RAMs- Fast interfaces to external high-performance RAMs• Flexible architecture that balances speed and density- Dedicated carry logic for high-speed arithmetic- Dedicated multiplier support- Cascade chain for wide-input functions- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset- Internal 3-state bussing- IEEE 1149.1 boundary-scan logic- Die-temperature sensor diode• Supported by FPGA Foundation™ and AllianceDevelopment Systems- Complete support for Unified Libraries, RelationallyPlaced Macros, and Design Manager- Wide selection of PC and workstation platforms• SRAM-based in-system configuration- Unlimited re-programmability- Four programming modes• 0.22 μm 5-layer metal process• 100% factory tested | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1.The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.• SelectIO™ signaling- Up to 633 I/O pins- Eighteen single-ended signal standards- Eight differential signal standards including LVDSand RSDS- Double Data Rate (DDR) support• Logic resources- Abundant logic cells with shift register capability- Wide multiplexers- Fast look-ahead carry logic- Dedicated 18 x 18 multipliers- JTAG logic compatible with IEEE 1149.1/1532• SelectRAM™ hierarchical memory- Up to 1,728 Kbits of total block RAM- Up to 432 Kbits of total distributed RAM• Digital Clock Manager (four DCMs)- Clock skew elimination- Frequency synthesis- High-resolution phase shifting | OTHER | In Stock | New Sealed Under Guarantee | | |
| | he Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,XCS05 approach and in many cases are equivalent to mask programmed ASIC devices.By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. In-System Programmable PROMs for Configuration of Xilinx® FPGAs• Low-Power Advanced CMOS NOR Flash Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (–40°C to +85°C)• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing• JTAG Command Initiation of Standard FPGA Configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Xilinx® Virtex® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at VCCINT = 0.85V, using -2LE devices, the speed specification for the L devices is the same as the -2I speed grade. When operated at VCCINT = 0.72V, the -2LE performance and static and dynamic power is reduced.DC and AC characteristics are specified in extended (E), industrial (I), and military (M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range. Absolute Maximum RatingsRecommended Operating ConditionsDC Characteristics Over Recommended Operating ConditionsQuiescent Supply CurrentThe recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements.For devices with HBM, the HBM power supplies can be powered on/off after or in-parallel with the core power supplies. The required power-on sequence is VCCAUX_HBM and VCCINT_IO followed by VCC_HBM/VCC_IO_HBM. VCC_IO_HBM must be connected to VCC_HBM. VCCAUX_HBM must be equal to or higher than VCC_HBM at all times.The recommended power-off sequence is the reverse of the power-on sequence. The recommended power-on sequence to achieve minimum current draw for the GTY or GTM transceivers is VCCINT, VCCINT_GT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VCCINT_GT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. When VCCINT and VCCINT_GT have the same recommended operating conditions, VCCINT and VCCINT_GT can be connected to the same power regulation circuit. When VCCINT and VCCINT_GT are connected to separate regulation circuits, VCCINT_GT must be within the recommended operating condition before device configuration.The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,XCS05 approach and in many cases are equivalent to mask programmed ASIC devices.By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. In-System Programmable PROMs for Configuration of Xilinx® FPGAs• Low-Power Advanced CMOS NOR Flash Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (–40°C to +85°C)• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing• JTAG Command Initiation of Standard FPGA Configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability Five platforms LX, LXT, SXT, TXT, and FXTVirtex-5 LX: High-performance general logic applicationsVirtex-5 LXT: High-performance logic with advanced serial connectivityVirtex-5 SXT: High-performance signal processing applications with advanced serial connectivityVirtex-5 TXT: High-performance systems with double density advanced serial connectivityVirtex-5 FXT: High-performance embedded systems with advanced serial connectivityCross-platform compatibilityLXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulatorsMost advanced, high-performance, optimal-utilization, FPGA fabricReal 6-input look-up table (LUT) technologyDual 5-LUT optionImproved reduced-hop routing64-bit distributed RAM optionSRL32/Dual SRL16 optionPowerful clock management tile (CMT) clockingDigital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shiftingPLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division36-Kbit block RAM/FIFOsTrue dual-port RAM blocksEnhanced optional programmable FIFO logicProgrammableTrue dual-port widths up to x36Simple dual-port widths up to x72Built-in optional error-correction circuitryOptionally program each block as two independent 18-Kbit blocksHigh-performance parallel SelectIO technology1.2 to 3.3V I/O OperationSource-synchronous interfacing using ChipSync™ technologyDigitally-controlled impedance (DCI) active terminationFlexible fine-grained I/O bankingHigh-speed memory interface supportAdvanced DSP48E slices25 x 18, two’s complement, multiplicationOptional adder, subtracter, and accumulatorOptional pipeliningOptional bitwise logical functionalityDedicated cascade connectionsFlexible configuration optionsSPI and Parallel FLASH interfaceMulti-bitstream support with dedicated fallback reconfiguration logicAuto bus width detection capabilitySystem Monitoring capability on all devicesOn-chip/Off-chip thermal monitoringOn-chip/Off-chip power supply monitoringJTAG access to all monitored quantitiesIntegrated Endpoint blocks for PCI Express DesignsLXT, SXT, TXT, and FXT PlatformsCompliant with the PCI Express Base Specification 1.1X1, x4, or x8 lane support per blockWorks in conjunction with RocketIO™ transceiversTri-mode 10/100/1000 Mb/s Ethernet MACsLXT, SXT, TXT, and FXT PlatformsRocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) optionsRocketIO GTP transceivers 100 Mb/s to 3.75 Gb/sLXT and SXT PlatformsRocketIO GTX transceivers 150 Mb/s to 6.5 Gb/sTXT and FXT PlatformsPowerPC 440 MicroprocessorsFXT Platform onlyRISC architecture7-stage pipeline32-Kbyte instruction and data caches includedOptimized processor interface structure (crossbar)65-nm copper CMOS process technology1.0V core voltageHigh signal-integrity flip-chip packaging available in standard or Pb-free package options | OTHER | In Stock | New Sealed Under Guarantee | | |
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| XC17S30XLPD8C |
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| CPLDs (Complex Programmable Logic Devices) |
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| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.Optimized for 1.8V systems- As fast as 7.1 ns pin-to-pin delays- As low as 14 μA quiescent current• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis- Multi-voltage I/O operation — 1.5V to 3.3V• Available in multiple package options- 208-pin PQFP with 173 user I/O- 256-ball FT (1.0mm) BGA with 212 user I/O- 324-ball FG (1.0mm) BGA with 270 user I/O- Pb-free available for all packages• Advanced system features- Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt-trigger input (per pin)- Unsurpassed low power management· DataGATE enable signal control- Four separate I/O banks- RealDigital 100% CMOS product term generation- Flexible clocking modes· Optional DualEDGE triggered registers· Clock divider (divide by 2,4,6,8,10,12,14,16)· CoolCLOCK- Global signal options with macrocell control· Multiple global clocks with phase selection permacrocell· Multiple global output enables· Global set/reset- Advanced design security- PLA architecture· Superior pinout retention· 100% product term routability across function block- Open-drain output option for Wired-OR and LED drive- Optional bus-hold, 3-state or weak pullup on selected I/O pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility- Hot Pluggable | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improvedThis device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK featureDataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.Table 1: I/O Standards for XC2C128(1)IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTTLVTTL3.33.3N/AN/ALVCMOS333.33.3N/AN/ALVCMOS252.52.5N/AN/ALVCMOS181.81.8N/AN/ALVCMOS15(2)1.51.5N/AN/AHSTL_11.51.50.750.75SSTL2_12.52.51.251.25SSTL3_13.33.31.51.5 Optimized for 1.8V systems- As fast as 5.7 ns pin-to-pin delays- As low as 13 μA quiescent current• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis.Refer to the CoolRunner™-II family data sheet forarchitecture description.- Multi-voltage I/O operation — 1.5V to 3.3V• Available in multiple package options- 100-pin VQFP with 80 user I/O- 144-pin TQFP with 118 user I/O- 132-ball CP (0.5mm) BGA with 106 user I/O- 208-pin PQFP with 173 user I/O- 256-ball FT (1.0mm) BGA with 184 user I/O- Pb-free available for all packages | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Spartan-6 Family:Spartan-6 LX FPGA: Logic optimizedSpartan-6 LXT FPGA: High-speed serial connectivityDesigned for low costMultiple efficient integrated blocksOptimized selection of I/O standardsStaggered padsHigh-volume plastic wire-bonded packagesLow static and dynamic power45 nm process optimized for cost and low powerHibernate power-down mode for zero powerSuspend mode maintains state and configuration with multi-pin wake-up, control enhancementLower-power 1.0V core voltage (LX FPGAs, -1L only)High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)Multi-voltage, multi-standard SelectIO™ interface banksUp to 1,080 Mb/s data transfer rate per differential I/OSelectable output drive, up to 24 mA per pin3.3V to 1.2V I/O standards and protocolsLow-cost HSTL and SSTL memory interfacesHot swap complianceAdjustable I/O slew rates to improve signal integrityHigh-speed GTP serial transceivers in the LXT FPGAsUp to 3.2 Gb/sHigh-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUIIntegrated Endpoint block for PCI Express designs (LXT)Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.Efficient DSP48A1 slicesHigh-performance arithmetic and signal processingFast 18 x 18 multiplier and 48-bit accumulatorPipelining and cascading capabilityPre-adder to assist filter applicationsIntegrated Memory Controller blocksDDR, DDR2, DDR3, and LPDDR supportData rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)Multi-port bus structure with independent FIFO to reduce design timing issuesAbundant logic resources with increased logic capacityOptional shift register or distributed RAM supportEfficient 6-input LUTs improve performance and minimize powerLUT with dual flip-flops for pipeline centric applicationsBlock RAM with a wide range of granularityFast block RAM with byte write enable18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMsClock Management Tile (CMT) for enhanced performanceLow noise, flexible clockingDigital Clock Managers (DCMs) eliminate clock skew and duty cycle distortionPhase-Locked Loops (PLLs) for low-jitter clockingFrequency synthesis with simultaneous multiplication, division, and phase shiftingSixteen low-skew global clock networksSimplified configuration, supports low-cost standards2-pin auto-detect configurationBroad third-party SPI (up to x4) and NOR flash supportFeature rich Xilinx Platform Flash with JTAGMultiBoot support for remote upgrade with multiple bitstreams, using watchdog protectionEnhanced security for design protectionUnique Device DNA identifier for design authenticationAES bitstream encryption in the larger devicesFaster embedded processing with enhanced, low cost, MicroBlaze™ soft processorIndustry-leading IP and reference designs | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the CoolRunner XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the CoolRunner XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.The CoolRunner XPLA3 family employs a full PLA structure for logic allocation within a function block. The PLA provides maximum flexibility and logic density, with superior pin locking capability, while maintaining deterministic timing.CoolRunner XPLA3 CPLDs are supported by Xilinx® WebPACK™ software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The CoolRunner XPLA3 family features also include the industry-standard, IEEE 1149.1, JTAG interface through which boundary-scan testing, In-System Programming (ISP), and reprogramming of the device can occur. The CoolRunner XPLA3 CPLD is electrically reprogrammable using industry standard device programmers.Fast Zero Power (FZP) design technique provides ultra-low power and very high speedTypical Standby Current of 17 to 18 μA at 25°CInnovative CoolRunner™ XPLA3 architecture combines high speed with extreme flexibilityBased on industry`s first TotalCMOS PLD — both CMOS design and process technologiesAdvanced 0.35μ five layer metal EEPROM process1,000 erase/program cycles guaranteed20 years data retention guaranteed3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interfaceFull Boundary-Scan Test (IEEE 1149.1)Fast programming timesSupport for complex asynchronous clocking16 product term clocks and four local control term clocks per function blockFour global clocks and one universal control term clock per deviceExcellent pin retention during design changesAvailable in commercial grade and extended voltage (2.7V to 3.6V) industrial grade5V tolerant I/O pinsInput register setup time of 2.5 nsSingle pass logic expandable to 48 product termsHigh-speed pin-to-pin delays of 5.0 nsSlew rate control per output100% routableSecurity bit prevents unauthorized accessSupports hot-plugging capabilityDesign entry/verification using Xilinx or industry standard CAE toolsInnovative Control Term structure provides:Asynchronous macrocell clockingAsynchronous macrocell register preset/resetClock enable control per macrocellFour output enable controls per function blockFoldback NAND for synthesis optimizationUniversal 3-state which facilitates "bed of nails" testingAvailable in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information. | OTHER | In Stock | New Sealed Under Guarantee | | |
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| | The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II Automotive 128-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade• Guaranteed to meet full electrical specifications over TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)• Optimized for 1.8V systems• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis- Multi-voltage I/O operation — 1.5V to 3.3V• Available in the following package options- 100-pin VQFP with 80 user I/O- 132-ball CP (0.5 mm) BGA with 100 user I/O- Pb-free only for all packages• Advanced system features- Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt-trigger input (per pin)- Unsurpassed low power management· DataGATE enable (DGE) signal control- Two separate I/O banks- RealDigital 100% CMOS product term generation- Flexible clocking modes· Optional DualEDGE triggered registers· Clock divider (divide by 2,4,6,8,10,12,14,16)· CoolCLOCK- Global signal options with macrocell control· Multiple global clocks with phase selection per macrocell· Multiple global output enables· Global set/reset- Advanced design security- Open-drain output option for Wired-OR and LED drive- PLA architecture· Superior pinout retention· 100% product term routability across function block- Optional bus-hold, 3-state or weak pull-up on selected I/O pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels- Hot pluggable | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XL device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx® Virtex®, Spartan®-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9500XL devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9500XL architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times. Optimized for high-performance 3.3V systems- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)- Pb-free available for all packages- Lower power operation- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS FastFLASH technology• Advanced system features- In-system programmable- Superior pin-locking and routability with FastCONNECT II switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with individual product-term allocation- Local clock inversion with three global and one product-term clocks- Individual output enable per output pin with local inversion- Input hysteresis on all user and boundary-scan pin inputs- Bus-hold circuitry on all user pin inputs- Supports hot-plugging capability- Full IEEE Std 1149.1 boundary-scan (JTAG)support on all devices• Four pin-compatible device densities- 36 to 288 macrocells, with 800 to 6400 usable gates• Fast concurrent programming• Slew rate control on individual outputs• Enhanced data security features• Excellent quality and reliability- 10,000 program/erase cycles endurance rating- 20 year data retention• Pin-compatible with 5V core XC9500 family in common package footprints | OTHER | In Stock | New Sealed Under Guarantee | | |
| Memory - Configuration Proms for FPGA's |
| | Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1, page 2). The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2, page 2).When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. Refer to "AC Electrical Characteristics," page 16 for timing considerations.A summary of the Platform Flash PROM family members and supported features is shown in Table 1.Table 1: Platform Flash PROM FeaturesDeviceDensity (Mb)VCCINT (V)VCCO Range (V)VCCO Range (V)PackagesProgram In-system via JTAGSerial Config.Parallel Config.Design RevisioningCompressionXCF01S13.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF02S23.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF04S43.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF08P81.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes(1) YesXCF16P161.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes YesXCF32P321.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes Yes | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1, page 2). The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2, page 2).When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. Refer to "AC Electrical Characteristics," page 16 for timing considerations.A summary of the Platform Flash PROM family members and supported features is shown in Table 1.Table 1: Platform Flash PROM FeaturesDeviceDensity (Mb)VCCINT (V)VCCO Range (V)VCCO Range (V)PackagesProgram In-system via JTAGSerial Config.Parallel Config.Design RevisioningCompressionXCF01S13.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF02S23.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF04S43.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF08P81.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes(1) YesXCF16P161.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes YesXCF32P321.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes Yes In-System Programmable PROMs for Configuration of Xilinx® FPGAs• Low-Power Advanced CMOS NOR Flash Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (–40°C to +85°C)• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing• JTAG Command Initiation of Standard FPGA Configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family. In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAsEndurance of 20,000 Program/Erase CyclesProgram/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)IEEE Std 1149.1 Boundary-Scan (JTAG) SupportJTAG Command Initiation of Standard FPGA ConfigurationSimple Interface to the FPGACascadable for Storing Longer or Multiple BitstreamsLow-Power Advanced CMOS FLASH ProcessDual Configuration ModesSerial Slow/Fast Configuration (up to 33 MHz)Parallel (up to 264 Mb/s at 33 MHz)5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals3.3V or 2.5V Output CapabilityDesign Support Using the Xilinx ISE™ Foundation™ Software PackagesAvailable in PC20, SO20, PC44, and VQ44 PackagesLead-Free (Pb-Free) Packaging | OTHER | In Stock | New Sealed Under Guarantee | | |
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| Touch Screen Controllers |
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| | Features• High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz• Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates• 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range• Enhanced pin-locking architecture• Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals - Extensive IEEE Std 1149.1 boundary-scan (JTAG) support - Programmable power reduction mode in each macrocell - Slew rate control on individual outputs - User programmable ground pin capability - Extended pattern security features for design protection - High-drive 24 mA outputs - 3.3V or 5V I/O capability - Advanced CMOS 5V FastFLASH™ technology - Supports parallel programming of multiple XC9500 devicesDescriptionThe XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint.The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades.Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be configured for 3.3V or 5V operation. All outputs provide 24 mA drive.144 macrocells with 3,200 usable gatesAvailable in small footprint packages100-pin TQFP (81 user I/O pins)144-pin TQFP (117 user I/O pins)144-pin CSP (117 user I/O pins)Optimized for high-performance 2.5V systemsLow power operationMulti-voltage operationAdvanced system featuresIn-system programmableTwo separate output banksSuperior pin-locking and routability with Fast CONNECT™ II switch matrixExtra wide 54-input Function BlocksUp to 90 product-terms per macrocell with individual product-term allocationLocal clock inversion with three global and one product-term clocksIndividual output enable per output pinInput hysteresis on all user and boundary-scan pin inputsBus-hold ciruitry on all user pin inputsFull IEEE Standard 1149.1 boundary-scan (JTAG)Fast concurrent programmingSlew rate control on individual outputsEnhanced data security featuresExcellent quality and reliability20 year data retentionESD protection exceeding 2,000V | OTHER | In Stock | New Sealed Under Guarantee | | |
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| System On Chip (SoC) |
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