All
      0
      Cart

      • OTHER

      • Popular
      • Newest
      • Most reviews

      CPLDs (Complex Programmable Logic Devices)

      CPLDs (Complex Programmable Logic Devices)
      ModelDescriptionBrandLeadingConditionPriceAction
      CPLDs (Complex Programmable Logic Devices)
      EPM7128SLC84-10
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      EPM240ZM68I8N
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064LI68-15
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064AETC44-7N
      General DescriptionMAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71■ Enhanced ISP features– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)– Pull-up resistor on I/O pins during in-system programming■ Pin-compatible with the popular 5.0-V MAX 7000S devices■ High-density PLDs ranging from 600 to 10,000 usable gates■ Extended temperature range■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages■ Supports hot-socketing in MAX 7000AE devices■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ PCI-compatible■ Bus-friendly architecture, including programmable slew-rate control■ Open-drain output option■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls■ Programmable power-up states for macrocell registers in MAX 7000AE devices■ Programmable power-saving mode for 50% or greater power reduction in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ 6 to 10 pin- or logic-driven output enable signals■ Two global clock signals with optional inversion■ Enhanced interconnect resources for improved routability■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers■ Programmable output slew-rate control■ Programmable ground pins
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064-TC44-7
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.Features...■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices– The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064STC44-7
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.Features...■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices– The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      EPM3064ATC44-7
      General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX®architecture (see Table 1)■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pinsduring in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ Industrial temperature range■ PCI compatible■ Bus–friendly architecture including programmable slew–rate control■ Open–drain output option■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power–saving mode for a power reduction of over 50%in each macrocell■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ Enhanced architectural features, including:– 6 or 10 pin– or logic–driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Programmable output slew–rate control■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)
      		OTHERIn StockNew Sealed Under Guarantee
      EPM3032ATC44-10
      General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX®architecture (see Table 1)■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pinsduring in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ Industrial temperature range■ PCI compatible■ Bus–friendly architecture including programmable slew–rate control■ Open–drain output option■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power–saving mode for a power reduction of over 50%in each macrocell■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ Enhanced architectural features, including:– 6 or 10 pin– or logic–driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Programmable output slew–rate control■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064LC447
      DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.Features■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX®architecture■ 5.0-V in-system programmability(ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064AELC44-7
      General DescriptionMAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71■ Enhanced ISP features– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)– Pull-up resistor on I/O pins during in-system programming■ Pin-compatible with the popular 5.0-V MAX 7000S devices■ High-density PLDs ranging from 600 to 10,000 usable gates■ Extended temperature range■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages■ Supports hot-socketing in MAX 7000AE devices■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ PCI-compatible■ Bus-friendly architecture, including programmable slew-rate control■ Open-drain output option■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls■ Programmable power-up states for macrocell registers in MAX 7000AE devices■ Programmable power-saving mode for 50% or greater power reduction in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ 6 to 10 pin- or logic-driven output enable signals■ Two global clock signals with optional inversion■ Enhanced interconnect resources for improved routability■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers■ Programmable output slew-rate control■ Programmable ground pins
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7064SLC44-7N
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      EPM3064ALI44-10N
      General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture.Features...■ High–performance, low–cost CMOS EEPROM–based programmablelogic devices (PLDs) built on a MAX® architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built–inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface withadvanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant withIEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pins during in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V,while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logiclevels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier(PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structurefor fast, predictable performance■ Industrial temperature range (Continue ...)
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7032AELC44-10
      The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
      		OTHERIn StockNew Sealed Under Guarantee
      EPM7032LI44-12
      General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices
      		OTHERIn StockNew Sealed Under Guarantee
      AFB1224SH-G620 R14006144
      		OTHERIn StockNew Sealed Under Guarantee
      0.549281s