| FPGAs (Field Programmable Gate Array) |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionAltera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources.Features...■ Low-cost, high-density, register-rich CMOS programmable logicdevice (PLD) family (see Table 1)– 2,500 to 16,000 usable gates– 282 to 1,500 registers■ System-level features– In-circuit reconfigurability (ICR) via external configurationdevices or intelligent controller– Fully compliant with the peripheral component interconnectSpecial Interest Group (PCI SIG) PCI Local Bus Specification,Revision 2.2 for 5.0-V operation– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)circuitry compliant with IEEE Std. 1149.1-1990 on selected devices– MultiVoltTM I/O interface enabling device core to run at 5.0 V,while I/O pins are compatible with 5.0-V and 3.3-V logic levels– Low power consumption (typical specification is 0.5 mA or less instandby mode)■ Flexible interconnect– FastTrack® Interconnect continuous routing structure for fast,predictable interconnect delays– Dedicated carry chain that implements arithmetic functions suchas fast adders, counters, and comparators (automatically used bysoftware tools and megafunctions)– Dedicated cascade chain that implements high-speed, high-fan-inlogic functions (automatically used by software tools andmegafunctions)– Tri-state emulation that implements internal tri-state nets■ Powerful I/O pins■ Programmable output slew-rate control reduces switching noise■ Peripheral register for fast setup and clock-to-output delay■ Fabricated on an advanced SRAM process■ Available in a variety of packages with 84 to 304 pins (see Table 2)■ Software design support and automatic place-and-route provided bythe Altera® MAX+PLUS® II development system for Windows-basedPCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBMRISC System/6000 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, Synplicity, and Veribest | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Cyclone III Device Family OverviewCyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:■ Cyclone III—lowest power, high functionality with the lowest cost■ Cyclone III LS—lowest power FPGAs with securityWith densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.This chapter contains the following sections:■ “Cyclone III Device Family Features” on page 1–1■ “Cyclone III Device Family Architecture” on page 1–6■ “Reference and Ordering Information” on page 1–12 | OTHER | In Stock | New Sealed Under Guarantee | | |
| | [ALTERA]Overview for the Arria II Device FamilyThe Arria® II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express® (PCIe®), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus® II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.Arria II Device FeatureThe Arria II device features consist of the following highlights:■ 40-nm, low-power FPGA engine■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry■ Eight-input fracturable look-up table (LUT)■ Memory logic array blocks (MLABs) for efficient implementation of small FIFOs■ High-performance digital signal processing (DSP) blocks up to 550 MHz■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers as well as 18 x 36-bit high-precision multiplier■ Hardcoded adders, subtractors, accumulators, and summation functions■ Fully-integrated design flow with the MATLAB and DSP Builder software from Altera■ Maximum system bandwidth■ Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 600 Mbps and 6.375 Gbps■ Dedicated circuitry to support physical layer functionality for popular serialprotocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, SerialRapidIO® (SRIO), Common Public Radio Interface (CPRI), OBSAI,SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter(JESD204), and SFI-5.■ Complete PIPE protocol solution with an embedded hard IP block that provides physical interface and media access control (PHY/MAC) layer, Data Link layer, and Transaction layer functionality■ Optimized for high-bandwidth system interfaces■ Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a wide range of single-ended and differential I/O standards■ High-speed LVDS I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to 1.25 Gbps■ Low power■ Architectural power reduction techniques■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps.■ Power optimizations integrated into the Quartus II development software■ Advanced usability and security features■ Parallel and serial configuration options■ On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for single-ended I/Os and on-chip differential (RD) termination for differential I/O■ 256-bit advanced encryption standard (AES) programming file encryption for design security with volatile and non-volatile key storage options■ Robust portfolio of IP for processing, serial protocols, and memory interfaces■ Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC)■ Emulated LVDS output support with a data rate of up to 1152 Mbps | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.The Stratix IV device family contains three optimized variants to meet different application requirements:■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 GbpsThe following list summarizes the Stratix IV device family features:■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality | OTHER | In Stock | New Sealed Under Guarantee | | |
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| | The Stratix® III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace.Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs.Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs: ■ The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. ■ The Stratix III E family is memory- and multiplier-rich for data-centric applications.Stratix III devices offer the following features:■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity■ Programmable Power Technology, which minimizes power while maximizing device performance | OTHER | In Stock | New Sealed Under Guarantee | | |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The NEC TOKIN’s Miniature Relays have evolved in response to various demands.Communication equipment, measurement instrument, FA equipment, electric home appliances and automotive electronics, and all the rest. In line with the increasing range of functions and downsizing of the various equipments, miniature relays have to respond to the demands of not only high performance and reliability, but also downsizing, low profile and environment resistance.NEC TOKIN uses the state-of-the-art technologies based on the integration of mechatronics and electronics, and has timely released excellent products. These are Miniature Signal Relays and Power Relays. They are ultra miniature and lightweight, and are suitable for high density packaging. In 2009 NEC TOKIN reached the 4 billion mark in the number of relays shipped and is updating the record daily now.NEC TOKIN provides the best-seller products already used for various applications, and variety of products such as a flat type for low profile mounting, a slim type for high density mounting, low power consumption type and excellent environment resistance type.• Compact, lightweight, ultra-low profile with high density• The low power consumption• Extremely durable plastic sealing• Small but high withstanding voltage• Lineup of SMTs (surface mount type) also available | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Overview for the Arria II Device FamilyThe Arria® II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express® (PCIe®), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus® II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.Arria II Device FeatureThe Arria II device features consist of the following highlights:■ 40-nm, low-power FPGA engine■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry■ Eight-input fracturable look-up table (LUT)■ Memory logic array blocks (MLABs) for efficient implementation of small FIFOs■ High-performance digital signal processing (DSP) blocks up to 550 MHz■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers as well as 18 x 36-bit high-precision multiplier■ Hardcoded adders, subtractors, accumulators, and summation functions■ Fully-integrated design flow with the MATLAB and DSP Builder software from Altera■ Maximum system bandwidth■ Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 600 Mbps and 6.375 Gbps■ Dedicated circuitry to support physical layer functionality for popular serialprotocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, SerialRapidIO® (SRIO), Common Public Radio Interface (CPRI), OBSAI,SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter(JESD204), and SFI-5.■ Complete PIPE protocol solution with an embedded hard IP block that provides physical interface and media access control (PHY/MAC) layer, Data Link layer, and Transaction layer functionality■ Optimized for high-bandwidth system interfaces■ Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a wide range of single-ended and differential I/O standards■ High-speed LVDS I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to 1.25 Gbps■ Low power■ Architectural power reduction techniques■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps.■ Power optimizations integrated into the Quartus II development software■ Advanced usability and security features■ Parallel and serial configuration options■ On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for single-ended I/Os and on-chip differential (RD) termination for differential I/O■ 256-bit advanced encryption standard (AES) programming file encryption for design security with volatile and non-volatile key storage options■ Robust portfolio of IP for processing, serial protocols, and memory interfaces■ Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC)■ Emulated LVDS output support with a data rate of up to 1152 Mbps | OTHER | In Stock | New Sealed Under Guarantee | | |
| | Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.Cyclone IV Device Family FeaturesThe Cyclone IV device family offers the following features:■ Low-cost, low-power FPGA fabric:■ 6K to 150K logic elements■ Up to 6.3 Mb of embedded memory■ Up to 360 18 × 18 multipliers for DSP processing intensive applications■ Protocol bridging applications for under 1.5 W total power■ Cyclone IV GX devices offer up to eight high-speed transceivers that provide:■ Data rates up to 3.125 Gbps■ 8B/10B encoder/decoder■ 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface■ Byte serializer/deserializer (SERDES)■ Word aligner■ Rate matching FIFO■ TX bit slipper for Common Public Radio Interface (CPRI)■ Electrical idle■ Dynamic channel reconfiguration allowing you to change data rates andprotocols on-the-fly■ Static equalization and pre-emphasis for superior signal integrity■ 150 mW per channel power consumption■ Flexible clocking structure to support multiple protocols in a single transceiver block■ Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1:■ ×1, ×2, and ×4 lane configurations■ End-point and root-port configurations■ Up to 256-byte payload■ One virtual channel■ 2 KB retry buffer■ 4 KB receiver (Rx) buffer■ Cyclone IV GX devices offer a wide range of protocol support:■ PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)■ Gigabit Ethernet (1.25 Gbps)■ CPRI (up to 3.072 Gbps)■ XAUI (3.125 Gbps)■ Triple rate serial digital interface (SDI) (up to 2.97 Gbps)■ Serial RapidIO (3.125 Gbps)■ Basic mode (up to 3.125 Gbps)■ V-by-One (up to 3.0 Gbps)■ DisplayPort (2.7 Gbps)■ Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)■ OBSAI (up to 3.072 Gbps)■ Up to 532 user I/Os■ LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx■ Support for DDR2 SDRAM interfaces up to 200 MHz■ Support for QDRII SRAM and DDR SDRAM up to 167 MHz■ Up to eight phase-locked loops (PLLs) per device■ Offered in commercial and industrial temperature grades | OTHER | In Stock | New Sealed Under Guarantee | | |
| | IntroductionFollowing the immensely successful first-generation Cyclone® device family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost.Features The Cyclone II device family offers the following features:■ High-density architecture with 4,608 to 68,416 LEs● M4K embedded memory blocks● Up to 1.1 Mbits of RAM available without reducing available logic● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes● Byte enables for data input masking during writes● Up to 260-MHz operation■ Embedded multipliers● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance● Optional input and output registers■ Advanced I/O support● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function● 133-MHz PCI-X 1.0 specification compatibility● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register● Programmable bus-hold feature● Programmable output drive strength feature● Programmable delays from the pin to the IOE or logic array● I/O bank grouping for unique VCCIO and/or VREF bank settings● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces● Hot-socketing operation support● Tri-state with weak pull-up on I/O pins before and during configuration● Programmable open-drain outputs● Series on-chip termination support | OTHER | In Stock | New Sealed Under Guarantee | | |
| | IntroductionFollowing the immensely successful first-generation Cyclone® device family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost.Features The Cyclone II device family offers the following features:■ High-density architecture with 4,608 to 68,416 LEs● M4K embedded memory blocks● Up to 1.1 Mbits of RAM available without reducing available logic● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes● Byte enables for data input masking during writes● Up to 260-MHz operation■ Embedded multipliers● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance● Optional input and output registers■ Advanced I/O support● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function● 133-MHz PCI-X 1.0 specification compatibility● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register● Programmable bus-hold feature● Programmable output drive strength feature● Programmable delays from the pin to the IOE or logic array● I/O bank grouping for unique VCCIO and/or VREF bank settings● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces● Hot-socketing operation support● Tri-state with weak pull-up on I/O pins before and during configuration● Programmable open-drain outputs● Series on-chip termination support | OTHER | In Stock | New Sealed Under Guarantee | | |
| | IntroductionFollowing the immensely successful first-generation Cyclone® device family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost.Features The Cyclone II device family offers the following features:■ High-density architecture with 4,608 to 68,416 LEs● M4K embedded memory blocks● Up to 1.1 Mbits of RAM available without reducing available logic● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes● Byte enables for data input masking during writes● Up to 260-MHz operation■ Embedded multipliers● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance● Optional input and output registers■ Advanced I/O support● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function● 133-MHz PCI-X 1.0 specification compatibility● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register● Programmable bus-hold feature● Programmable output drive strength feature● Programmable delays from the pin to the IOE or logic array● I/O bank grouping for unique VCCIO and/or VREF bank settings● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces● Hot-socketing operation support● Tri-state with weak pull-up on I/O pins before and during configuration● Programmable open-drain outputs● Series on-chip termination support | OTHER | In Stock | New Sealed Under Guarantee | | |
| | IntroductionThe Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions.FeaturesThe Stratix II family offers the following features:■ 15,600 to 179,400 equivalent LEs; see Table 1–1■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters■ Up to 16 global clocks with 24 clocking resources per device region■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting■ Support for numerous single-ended and differential I/O standards■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions■ Support for design security using configuration bitstream encryption■ Support for remote configuration updates | OTHER | In Stock | New Sealed Under Guarantee | | |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| | This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices■ Easy-to-use four-pin interface■ Low current during configuration and near-zero standby mode current■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers■ Available in compact plastic packages■ 8-pin plastic dual in-line (PDIP) package■ 20-pin plastic J-lead chip carrier (PLCC) package■ 32-pin plastic thin quad flat pack (TQFP) package■ EPC2 device has reprogrammable flash configuration memory■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration | OTHER | In Stock | New Sealed Under Guarantee | | |
| |
| Memory - Configuration Proms for FPGA's |
| | Functional DescriptionWith SRAM-based devices that support active serial configuration, configuration data must be reloaded each time the device powers up, the system reconfigures, or when new configuration data is required. Serial configuration devices are flash memory devices with a serial interface that can store configuration data for FPGA devices that support active serial configuration and reload the data to the device upon power-up or reconfiguration. Table 3–1 summarizes the features of the Altera configuration devices and the amount of configuration space they hold.FeaturesThe serial configuration devices provide the following features:■ 1-, 4-, 16-, 64-, and 128-Mbit flash memory devices that serially configure Arria® series, Cyclone® series, all device families in the Stratix® series except the Stratix device family, and FPGAs using the active serial (AS) configuration scheme■ Easy-to-use four-pin interface■ Low cost, low-pin count, and non-volatile memory■ Low current during configuration and near-zero standby mode current■ 2.7-V to 3.6-V operation■ EPCS1 and EPCS4 available in 8-pin small outline integrated circuit (SOIC) package. EPCS16 available in 8-pin or 16-pin SOIC packages. EPCS64 and EPCS128 available in 16-pin SOIC package■ Enables the Nios® processor to access unused flash memory through AS memory interface■ Re-programmable memory with more than 100,000 erase/program cycles■ Write protection support for memory sectors using status register bits■ In-system programming support with SRunner software driver■ In-system programming support with USB Blaster™, EthernetBlaster, or ByteBlaster™ II download cables■ Additional programming support with the Altera® Programming Unit (APU) and programming hardware from BP Microsystems, System General, and other vendors■ Delivered with the memory array erased (all the bits set to 1) | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to storeprocessor code or data that can be accessed via the external flash interface after FPGA configuration is complete.Features■ Enhanced configuration devices include EPC4, EPC8, and EPC16 devices■ Single-chip configuration solution for Stratix® series, Cyclone™ series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury™, ACEX® 1K, and FLEX® 10K (FLEX 10KE and FLEX 10KA) devices■ Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage● On-chip decompression feature almost doubles the effective configuration density■ Standard flash die and a controller die combined into single stacked chip package■ External flash interface supports parallel programming of flash and external processor access to unused portions of memory● Flash memory block/sector protection capability via external flash interface● Supported in EPC16 and EPC4 devices■ Page mode support for remote and local reconfiguration with up to eight configurations for the entire system● Compatible with Stratix series Remote System Configuration feature■ Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle■ Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs■ Pin-selectable 2-ms or 100-ms power-on reset (POR) time■ Configuration clock supports programmable input source and frequency synthesis● Multiple configuration clock sources supported (internal oscillator and external clock input pin)● External clock source with frequencies up to 133 MHz● Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz● Clock synthesis supported via user programmable divide counter■ Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA® packages● Vertical migration between all devices supported in the 100-pin PQFP package■ Supply voltage of 3.3 V (core and I/O) | OTHER | In Stock | New Sealed Under Guarantee | | |
| | AFB0924HH-A DELTA Delta AFB FAN 92x92x25mm ,Size(MM) 92*92*25,Voltage(V) 24,Operating Voltage(V) 14.0 to 27.6,Rated Current(A) 0.13,Power(W) 3.12,Speed(RPM) 3200,Max Air Flow(CFM) 57.92,Max Air Pressure(IN H2O) 0.221,Noise(dB) 38,Weight(g) 99,Bearing Ball | OTHER | In Stock | New Sealed Under Guarantee | | |
| | AFB0924VH-D002 DELTA Delta AFB FAN 92x92x25mm ,Size(MM) 92*92*25,Voltage(V) 24,Operating Voltage(V) 14.0 to 27.6,Rated Current(A) 0.22,Power(W) 5.28,Speed(RPM) 3800,Max Air Flow(CFM) 67.8,Max Air Pressure(IN H2O) 0.302,Noise(dB) 45,Weight(g) 99,Bearing Ball | OTHER | In Stock | New Sealed Under Guarantee | | |
| CPLDs (Complex Programmable Logic Devices) |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | IntroductionThe MAX®II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control. | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionMAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71■ Enhanced ISP features– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)– Pull-up resistor on I/O pins during in-system programming■ Pin-compatible with the popular 5.0-V MAX 7000S devices■ High-density PLDs ranging from 600 to 10,000 usable gates■ Extended temperature range■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages■ Supports hot-socketing in MAX 7000AE devices■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ PCI-compatible■ Bus-friendly architecture, including programmable slew-rate control■ Open-drain output option■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls■ Programmable power-up states for macrocell registers in MAX 7000AE devices■ Programmable power-saving mode for 50% or greater power reduction in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ 6 to 10 pin- or logic-driven output enable signals■ Two global clock signals with optional inversion■ Enhanced interconnect resources for improved routability■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers■ Programmable output slew-rate control■ Programmable ground pins | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.Features...■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices– The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.Features...■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices– The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX®architecture (see Table 1)■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pinsduring in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ Industrial temperature range■ PCI compatible■ Bus–friendly architecture including programmable slew–rate control■ Open–drain output option■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power–saving mode for a power reduction of over 50%in each macrocell■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ Enhanced architectural features, including:– 6 or 10 pin– or logic–driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Programmable output slew–rate control■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX®architecture (see Table 1)■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pinsduring in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ Industrial temperature range■ PCI compatible■ Bus–friendly architecture including programmable slew–rate control■ Open–drain output option■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls■ Programmable power–saving mode for a power reduction of over 50%in each macrocell■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ Enhanced architectural features, including:– 6 or 10 pin– or logic–driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Programmable output slew–rate control■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) | OTHER | In Stock | New Sealed Under Guarantee | | |
| | DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.Features■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX®architecture■ 5.0-V in-system programmability(ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)■ PCI-compliant devices available | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionMAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.Features...■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71■ Enhanced ISP features– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)– Pull-up resistor on I/O pins during in-system programming■ Pin-compatible with the popular 5.0-V MAX 7000S devices■ High-density PLDs ranging from 600 to 10,000 usable gates■ Extended temperature range■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages■ Supports hot-socketing in MAX 7000AE devices■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance■ PCI-compatible■ Bus-friendly architecture, including programmable slew-rate control■ Open-drain output option■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls■ Programmable power-up states for macrocell registers in MAX 7000AE devices■ Programmable power-saving mode for 50% or greater power reduction in each macrocell■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell■ Programmable security bit for protection of proprietary designs■ 6 to 10 pin- or logic-driven output enable signals■ Two global clock signals with optional inversion■ Enhanced interconnect resources for improved routability■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers■ Programmable output slew-rate control■ Programmable ground pins | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionMAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture.Features...■ High–performance, low–cost CMOS EEPROM–based programmablelogic devices (PLDs) built on a MAX® architecture (see Table 1)■ 3.3-V in-system programmability (ISP) through the built–inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface withadvanced pin-locking capability– ISP circuitry compliant with IEEE Std. 1532■ Built–in boundary-scan test (BST) circuitry compliant withIEEE Std. 1149.1-1990■ Enhanced ISP features:– Enhanced ISP algorithm for faster programming– ISP_Done bit to ensure complete programming– Pull-up resistor on I/O pins during in–system programming■ High–density PLDs ranging from 600 to 10,000 usable gates■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to227.3 MHz■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V,while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logiclevels■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier(PLCC), and FineLine BGATM packages■ Hot–socketing support■ Programmable interconnect array (PIA) continuous routing structurefor fast, predictable performance■ Industrial temperature range (Continue ...) | OTHER | In Stock | New Sealed Under Guarantee | | |
| | The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells | OTHER | In Stock | New Sealed Under Guarantee | | |
| | General DescriptionThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.Features...■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture■ 5.0-V in-system programmability (ISP) through the built-inIEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available inMAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000Sdevices■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000Sdevices with 128 or more macrocells■ Complete EPLD family with logic densities ranging from 600 to5,000 usable gates (see Tables 1 and 2)■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies (including interconnect)■ PCI-compliant devices available■ Open-drain output option in MAX 7000S devices■ Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls■ Programmable power-saving mode for a reduction of over 50% ineach macrocell■ Configurable expander product-term distribution, allowing up to32 product terms per macrocell■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramicpin-grid array (PGA), plastic quad flat pack (PQFP), power quad flatpack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages■ Programmable security bit for protection of proprietary designs■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices tointerface with 3.3-V or 5.0-V devices (MultiVolt I/O operation isnot available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000Bdevices■ Enhanced features available in MAX 7000E and MAX 7000S devices– Six pin- or logic-driven output enable signals– Two global clock signals with optional inversion– Enhanced interconnect resources for improved routability– Fast input setup times provided by a dedicated path from I/Opin to macrocell registers– Programmable output slew-rate control■ Software design support and automatic place-and-route provided byAltera’s development system for Windows-based PCs and SunSPARCstation, and HP 9000 Series 700/800 workstations■ Additional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),Verilog HDL, VHDL, and other interfaces to popular EDA tools frommanufacturers such as Cadence, Exemplar Logic, Mentor Graphics,OrCAD, Synopsys, and VeriBest■ Programming support– Altera’s Master Programming Unit (MPU) and programminghardware from third-party manufacturers program allMAX 7000 devices– The BitBlasterTM serial download cable, ByteBlasterMVTMparallel port download cable, and MasterBlasterTMserial/universal serial bus (USB) download cable program MAX7000S devices | OTHER | In Stock | New Sealed Under Guarantee | | |
| | AFB1224SH-G620 R14006144 DELTA Delta AFB FAN 120X120X25mm ,Size(MM) 120*120*25,Voltage(V) 24,Operating Voltage(V) 14.0 to 27.6,Rated Current(A) 0.28,Power(W) 6.72,Speed(RPM) 3400,Max Air Flow(CFM) 113.11,Max Air Pressure(IN H2O) 0.43,Noise(dB) 46.5,Weight(g) 198,Bearing Ball | OTHER | In Stock | New Sealed Under Guarantee | | |
