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      Micron

      Micron Memory Chips
      ModelDescriptionBrandLeadingConditionPriceAction
      Micron
      PE80252B1-000C-F99
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      Memory Chips
      M25PE80-VMW6TG
      DescriptionThe M25PE80 is an 8 Mbit (1 Mb × 8) Serial Paged Flash memory accessed by a high speed SPI-compatible bus.The memory can be written or programmed 1 to 256 Bytes at a time, using the Page Writeor Page Program instruction. The Page Write instruction consists of an integrated PageErase cycle followed by a Page Program cycle.The memory is organized as 16 sectors that are further divided up into 16 subsectors each(256 subsectors in total). Each sector contains 256 pages and each subsector contains 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1 048 576 bytes.Features■ SPI bus compatible serial interface■ 8-Mbit Page-Erasable Flash memory■ Page size: 256 bytes– Page Write in 11 ms (typical)– Page Program in 0.8 ms (typical)– Page Erase in 10 ms (typical)■ SubSector Erase (4 Kbytes)■ Sector Erase (64 Kbytes)■ Bulk Erase (8 Mbits)■ 2.7 V to 3.6 V single supply voltage■ 50 MHz clock rate (maximum)■ Deep Power-down mode 1 µA (typical)■ Electronic Signature– JEDEC standard two-byte signature(8014h)■ Software Write Protection on a 64 Kbyte sector basis■ Hardware Write Protection of the memory area selected using the BP0, BP1 and BP2 bits■ More than 100 000 Write cycles■ More than 20 year data retention■ Packages– ECOPACK® (RoHS compliant)
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      M25P10-AVMN6TP
      SUMMARY DESCRIPTIONThe M25Pxx is a 512Kbit to 32Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-com patible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as a number of sectors, each containing 256 or 128 pages. Each page is 256 bytes wide.FEATURES SUMMARY■ 512Kbit to 32Mbit of Flash Memory■ Page Program (up to 256 Bytes) in 1.4ms (typical)■ Sector Erase (256 Kbit or 512Kbit)■ Bulk Erase (512Kbit to 32Mbit)■ 2.7 to 3.6V Single Supply Voltage■ SPI Bus Compatible Serial Interface■ 40MHz to 50MHz Clock Rate (maximum)■ Deep Power-down Mode 1µA (typical)■ Electronic Signatures– JEDEC Standard Two-Byte Signature (20xxh)– RES Instruction, One-Byte, Signature, for backward compatibility■ More than 100000 Erase/Program Cycles per Sector■ More than 20 Year Data Retention
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      M25P20-VMN6TPB
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      N25Q032A13ESE40F
      Device DescriptionThe N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) func tionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.FeaturesThe memory is organized as 64 (64KB) main sectors that are further divided into 16 sub sectors each (1024 subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole.The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections The device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
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      N25Q064A13ESE40F
      Device DescriptionThe N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) func tionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.FeaturesThe memory is organized as 64 (64KB) main sectors that are further divided into 16 sub sectors each (1024 subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole.The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections The device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
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      PIC16F722AT-I/SS
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      MT29F1G08ABADAWP-IT:D
      General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#).This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densi ties with no board redesign.A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization.This device has an internal 4-bit ECC that can be enabled using the GET/SET features.See Internal ECC and Spare Area Mapping for ECC for more information.Features• Open NAND Flash Interface (ONFI) 1.0-compliant1• Single-level cell (SLC) technology• Organization– Page size x8: 2112 bytes (2048 + 64 bytes)– Page size x16: 1056 words (1024 + 32 words)– Block size: 64 pages (128K + 4K bytes)– Plane size: 2 planes x 2048 blocks per plane– Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks 16Gb: 16,384 blocks• Asynchronous I/O performance– tRC/tWC: 20ns (3.3V), 25ns (1.8V)• Array performance– Read page: 25µs 3– Program page: 200µs (TYP: 1.8V, 3.3V)3– Erase block: 700µs (TYP)• Command set: ONFI NAND Flash Protocol• Advanced command set– Program page cache mode4– Read page cache mode 4– One-time programmable (OTP) mode– Two-plane commands 4– Interleaved die (LUN) operations– Read unique ID– Block lock (1.8V only)– Internal data move• Operation status byte provides software method for detecting– Operation completion– Pass/fail condition– Write-protect status• Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion• WP# signal: Write protect entire device• First block (block address 00h) is valid when ship ped from factory with ECC. For minimum required ECC, see Error Management.• Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000• RESET (FFh) required as first command after power-on• Alternate method of device initialization (Nand_In it) after power up (contact factory)• Internal data move operations supported within the plane from which data is read• Quality and reliability– Data retention: 10 years– Endurance: 100,000 PROGRAM/ERASE cycles• Operating voltage range– VCC: 2.7–3.6V– VCC: 1.7–1.95V• Operating temperature:– Commercial: 0°C to +70°C– Industrial (IT): –40ºC to +85ºC• Package– 48-pin TSOP type 1, CPL2– 63-ball VFBGA
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      MT29F2G08ABAEAWP-IT:E
      General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-perform ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands,address, and data. There are five control signals used to implement the asyn chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#).Features• Open NAND Flash Interface (ONFI) 2.2-compliant1• Multiple-level cell (MLC) technology• Organization– Page size x8: 8640 bytes (8192 + 448 bytes)– Block size: 256 pages (2048K + 112K bytes)– Plane size: 2 planes x 2048 blocks per plane– Device size: 64Gb: 4096 blocks;128Gb: 8192 blocks;256Gb: 16,384 blocks;512Gb: 32,786 blocks• Synchronous I/O performance– Up to synchronous timing mode 5– Clock rate: 10ns (DDR)– Read/write throughput per pin: 200 MT/s• Asynchronous I/O performance– Up to asynchronous timing mode 5–tRC/tWC: 20ns (MIN)• Array performance– Read page: 50µs (MAX)– Program page: 1300µs (TYP)– Erase block: 3ms (TYP)• Operating Voltage Range– VCC: 2.7–3.6V– VCCQ: 1.7–1.95V, 2.7–3.6V• Command set: ONFI NAND Flash Protocol• Advanced Command Set– Program cache– Read cache sequential– Read cache random– One-time programmable (OTP) mode– Multi-plane commands– Multi-LUN operations– Read unique ID– Copyback• First block (block address 00h) is valid when shippedfrom factory. For minimum required ECC, seeError Management (page 109).• RESET (FFh) required as first command after poweron• Operation status byte provides software method fordetecting– Operation completion– Pass/fail condition– Write-protect status• Data strobe (DQS) signals provide a hardware methodfor synchronizing data DQ in the synchronousinterface• Copyback operations supported within the planefrom which data is read• Quality and reliability– Data retention: 10 years– Endurance: 5000 PROGRAM/ERASE cycles• Operating temperature:– Commercial: 0°C to +70°C– Industrial (IT): –40ºC to +85ºC• Package– 52-pad LGA– 48-pin TSOP– 100-ball BGA
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      PIC16F723A-I/SS
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      M25PE20-VMN6TP
      DescriptionThe M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) Serial Paged Flash memories, respectively. They are accessed by a high speed SPI-compatible bus.The memories can be written or programmed 1 to 256 Bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.Features■ 1 or 2 Mbit of Page-Erasable Flash memory■ 2.7 V to 3.6 V single supply voltage■ SPI bus compatible serial interface■ 50 MHz clock rate (maximum)■ Page size: 256 bytes– Page Write in 11 ms (typical)– Page Program in 0.8 ms (typical)– Page Erase in 10 ms (typical)■ SubSector Erase (32 Kbits)■ Sector Erase (512 Kbits)■ Bulk Erase (1 Mbit for the M25PE10, 2 Mbits for the M25PE20)■ Deep Power-down mode 1µA (typical)■ Electronic Signature– JEDEC Standard Two-Byte Signature(8012h for M25PE20 8011h for M25PE10)■ Software Write Protection on a 64 Kbyte sector basis■ More than 100 000 Write cycles■ More than 20 year data retention■ Hardware Write Protection of the memory area selected using the BP0 and BP1 bits■ Package– ECOPACK® (RoHS compliant)
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      MT29F2G08ABAEAH4-IT:E
      General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-perform ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands,address, and data. There are five control signals used to implement the asyn chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#).Features• Open NAND Flash Interface (ONFI) 2.2-compliant1• Multiple-level cell (MLC) technology• Organization– Page size x8: 8640 bytes (8192 + 448 bytes)– Block size: 256 pages (2048K + 112K bytes)– Plane size: 2 planes x 2048 blocks per plane– Device size: 64Gb: 4096 blocks;128Gb: 8192 blocks;256Gb: 16,384 blocks;512Gb: 32,786 blocks• Synchronous I/O performance– Up to synchronous timing mode 5– Clock rate: 10ns (DDR)– Read/write throughput per pin: 200 MT/s• Asynchronous I/O performance– Up to asynchronous timing mode 5–tRC/tWC: 20ns (MIN)• Array performance– Read page: 50µs (MAX)– Program page: 1300µs (TYP)– Erase block: 3ms (TYP)• Operating Voltage Range– VCC: 2.7–3.6V– VCCQ: 1.7–1.95V, 2.7–3.6V• Command set: ONFI NAND Flash Protocol• Advanced Command Set– Program cache– Read cache sequential– Read cache random– One-time programmable (OTP) mode– Multi-plane commands– Multi-LUN operations– Read unique ID– Copyback• First block (block address 00h) is valid when shippedfrom factory. For minimum required ECC, seeError Management (page 109).• RESET (FFh) required as first command after poweron• Operation status byte provides software method fordetecting– Operation completion– Pass/fail condition– Write-protect status• Data strobe (DQS) signals provide a hardware methodfor synchronizing data DQ in the synchronousinterface• Copyback operations supported within the planefrom which data is read• Quality and reliability– Data retention: 10 years– Endurance: 5000 PROGRAM/ERASE cycles• Operating temperature:– Commercial: 0°C to +70°C– Industrial (IT): –40ºC to +85ºC• Package– 52-pad LGA– 48-pin TSOP– 100-ball BGA
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      M29F400FB5AN6F2
      This description applies specifically to the M29F 16Mb (2 Meg x 8 or 1 Meg x 16) nonvolatile memory device, but also applies to lower densities. The device enables READ,ERASE, and PROGRAM operations using a single, low-voltage (4.5–5.5V) supply. Onpower-up, the device defaults to read mode and can be read in the same way as a ROMor EPROM.The device is divided into blocks that can be erased independently, preserving valid data while old data is erased. Each block can be protected independently to prevent accidental PROGRAM or ERASE operations from modifying the memory. PROGRAM andERASE commands are written to the command interface. An on-chip program/erasecontroller simplifies the process of programming or erasing the device by managing theoperations required to update the memory contents.The end of a PROGRAM or ERASE operation can be detected and any error conditionsidentified. The command set required to control the memory is consistent with JEDECstandards.The blocks are asymmetrically arranged. The first or last 64KB have been divided intofour additional blocks. The 16KB boot block can be used for small initialization code tostart the microprocessor. The two 8KB parameter blocks can be used for parameterstorage. The remaining 32KB is a small main block where the application may be stored.CE#, OE#, and WE# control the bus operation of the memory. They enable simple connection to most microprocessors, often without additional logic. Devices are offered in48-pin TSOP (12mm x 20mm) and 44-pin small-outline packages. The device is supplied with all the bits erased (set to 1).
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      MT41J128M16JT-093G:K
      DDR3 SDRAM2Gb: x4, x8, x16 DDR3 SDRAMFeatures• VDD= VDDQ= 1.5V ±0.075V• 1.5V center-terminated push/pull I/O• Differential bidirectional data strobe• 8n-bit prefetch architecture• Differential clock inputs (CK, CK#)• 8 internal banks• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals• Programmable CAS READ latency (CL)• Posted CAS additive latency (AL)• Programmable CAS WRITE latency (CWL) based on tCK• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])• Selectable BC4 or BL8 on-the-fly (OTF)• Self refresh mode• TC of 0°C to 95°C– 64ms, 8192 cycle refresh at 0°C to 85°C– 32ms, 8192 cycle refresh at 85°C to 95°C• Self refresh temperature (SRT)• Write leveling• Multipurpose register• Output driver calibration
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      MT29F2G01ABAGDWB-IT:G
      General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-perform ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands,address, and data. There are five control signals used to implement the asyn chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#).Features• Open NAND Flash Interface (ONFI) 2.2-compliant1• Multiple-level cell (MLC) technology• Organization– Page size x8: 8640 bytes (8192 + 448 bytes)– Block size: 256 pages (2048K + 112K bytes)– Plane size: 2 planes x 2048 blocks per plane– Device size: 64Gb: 4096 blocks;128Gb: 8192 blocks;256Gb: 16,384 blocks;512Gb: 32,786 blocks• Synchronous I/O performance– Up to synchronous timing mode 5– Clock rate: 10ns (DDR)– Read/write throughput per pin: 200 MT/s• Asynchronous I/O performance– Up to asynchronous timing mode 5–tRC/tWC: 20ns (MIN)• Array performance– Read page: 50µs (MAX)– Program page: 1300µs (TYP)– Erase block: 3ms (TYP)• Operating Voltage Range– VCC: 2.7–3.6V– VCCQ: 1.7–1.95V, 2.7–3.6V• Command set: ONFI NAND Flash Protocol• Advanced Command Set– Program cache– Read cache sequential– Read cache random– One-time programmable (OTP) mode– Multi-plane commands– Multi-LUN operations– Read unique ID– Copyback• First block (block address 00h) is valid when shippedfrom factory. For minimum required ECC, seeError Management (page 109).• RESET (FFh) required as first command after poweron• Operation status byte provides software method fordetecting– Operation completion– Pass/fail condition– Write-protect status• Data strobe (DQS) signals provide a hardware methodfor synchronizing data DQ in the synchronousinterface• Copyback operations supported within the planefrom which data is read• Quality and reliability– Data retention: 10 years– Endurance: 5000 PROGRAM/ERASE cycles• Operating temperature:– Commercial: 0°C to +70°C– Industrial (IT): –40ºC to +85ºC• Package– 52-pad LGA– 48-pin TSOP– 100-ball BGA
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      N25Q256A13ESF40F
      DescriptionThe N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.FeaturesThe memory is organized as 512 (64KB) main sectors that are further divided into 16 subsectors each (8192 subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole.The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protectionsThe device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command.The device also has the ability to pause and resume PROGRAM and ERASE cycles by us ing dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
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      MT47H32M16NF-25E IT:H
      DDR2 SDRAMMT47H256M4 – 32 Meg x 4 x 8 banksMT47H128M8 – 16 Meg x 8 x 8 banksMT47H64M16 – 8 Meg x 16 x 8 banksFeatures• VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V• JEDEC-standard 1.8V I/O (SSTL_18-compatible)• Differential data strobe (DQS, DQS#) option• 4n-bit prefetch architecture• Duplicate output strobe (RDQS) option for x8• DLL to align DQ and DQS transitions with CK• 8 internal banks for concurrent operation• Programmable CAS latency (CL)• Posted CAS additive latency (AL)• WRITE latency = READ latency - 1 tCK• Selectable burst lengths (BL): 4 or 8• Adjustable data-output drive strength• 64ms, 8192-cycle refresh• On-die termination (ODT)• Industrial temperature (IT) option• Automotive temperature (AT) option• RoHS-compliant• Supports JEDEC clock jitter specification
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      MT41K256M16HA-125:E
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      MT41K64M16TW-107 IT:J
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      MT41K128M16JT-125IT:K
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      MT41K128M16JT-107:KTR
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      1.948474s